WO2009094276A3 - Vertical outgassing channels - Google Patents
Vertical outgassing channels Download PDFInfo
- Publication number
- WO2009094276A3 WO2009094276A3 PCT/US2009/030997 US2009030997W WO2009094276A3 WO 2009094276 A3 WO2009094276 A3 WO 2009094276A3 US 2009030997 W US2009030997 W US 2009030997W WO 2009094276 A3 WO2009094276 A3 WO 2009094276A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- channels
- insulator
- box
- bonding surface
- buried oxide
- Prior art date
Links
- 238000010943 off-gassing Methods 0.000 title abstract 2
- 239000012212 insulator Substances 0.000 abstract 2
- 229910008051 Si-OH Inorganic materials 0.000 abstract 1
- 229910006358 Si—OH Inorganic materials 0.000 abstract 1
- 125000002887 hydroxy group Chemical group [H]O* 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
- 229910052760 oxygen Inorganic materials 0.000 abstract 1
- 239000001301 oxygen Substances 0.000 abstract 1
- -1 oxygen ions Chemical class 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
Abstract
InP epitaxial material is directly bonded onto a Silicon-On-Insulator (SOI) wafer having Vertical Outgassing Channels (VOCs) between the bonding surface and the insulator (buried oxide, or BOX) layer. H2O and other molecules near the bonding surface migrate to the closest VOC and are quenched in the buried oxide (BOX) layer quickly by combining with bridging oxygen ions and forming pairs of stable nonbridging hydroxyl groups (Si-OH). Various sizes and spacings of channels are envisioned for various devices.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN200980102158.7A CN101999165B (en) | 2008-01-14 | 2009-01-14 | Vertical outgassing channels |
EP09703836.8A EP2238614B1 (en) | 2008-01-14 | 2009-01-14 | Vertical outgassing channels |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US2092008P | 2008-01-14 | 2008-01-14 | |
US61/020,920 | 2008-01-14 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2009094276A2 WO2009094276A2 (en) | 2009-07-30 |
WO2009094276A3 true WO2009094276A3 (en) | 2009-09-17 |
Family
ID=40901599
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2009/030997 WO2009094276A2 (en) | 2008-01-14 | 2009-01-14 | Vertical outgassing channels |
Country Status (4)
Country | Link |
---|---|
US (3) | US8129257B2 (en) |
EP (1) | EP2238614B1 (en) |
CN (2) | CN101999165B (en) |
WO (1) | WO2009094276A2 (en) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8155666B2 (en) | 2008-06-16 | 2012-04-10 | Skyhook Wireless, Inc. | Methods and systems for determining location using a cellular and WLAN positioning system by selecting the best cellular positioning system solution |
US8941442B2 (en) | 2010-02-04 | 2015-01-27 | Honeywell International Inc. | Fabrication techniques to enhance pressure uniformity in anodically bonded vapor cells |
US8299860B2 (en) | 2010-02-04 | 2012-10-30 | Honeywell International Inc. | Fabrication techniques to enhance pressure uniformity in anodically bonded vapor cells |
US8729673B1 (en) * | 2011-09-21 | 2014-05-20 | Sandia Corporation | Structured wafer for device processing |
TW201401547A (en) * | 2012-06-19 | 2014-01-01 | Chi Mei Lighting Tech Corp | Fabricating method for light emitting diode |
CN105023877B (en) | 2014-04-28 | 2019-12-24 | 联华电子股份有限公司 | Semiconductor chip, package structure and manufacturing method thereof |
WO2016018288A1 (en) | 2014-07-30 | 2016-02-04 | Hewlett-Packard Development Company, L.P. | Hybrid multilayer device |
WO2016018285A1 (en) | 2014-07-30 | 2016-02-04 | Hewlett-Packard Development Company, L.P. | Optical waveguide resonators |
US9455179B1 (en) | 2015-07-09 | 2016-09-27 | International Business Machines Corporation | Methods to reduce debonding forces on flexible semiconductor films disposed on vapor-releasing adhesives |
US10658177B2 (en) | 2015-09-03 | 2020-05-19 | Hewlett Packard Enterprise Development Lp | Defect-free heterogeneous substrates |
WO2017123245A1 (en) | 2016-01-15 | 2017-07-20 | Hewlett Packard Enterprise Development Lp | Multilayer device |
US11088244B2 (en) | 2016-03-30 | 2021-08-10 | Hewlett Packard Enterprise Development Lp | Devices having substrates with selective airgap regions |
US10079471B2 (en) | 2016-07-08 | 2018-09-18 | Hewlett Packard Enterprise Development Lp | Bonding interface layer |
US10193634B2 (en) | 2016-09-19 | 2019-01-29 | Hewlett Packard Enterprise Development Lp | Optical driver circuits |
US10381801B1 (en) | 2018-04-26 | 2019-08-13 | Hewlett Packard Enterprise Development Lp | Device including structure over airgap |
US10541214B2 (en) * | 2018-04-27 | 2020-01-21 | Juniper Networks, Inc. | Enhanced bonding between III-V material and oxide material |
US20200075533A1 (en) | 2018-08-29 | 2020-03-05 | Invensas Bonding Technologies, Inc. | Bond enhancement in microelectronics by trapping contaminants and arresting cracks during direct-bonding processes |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6455398B1 (en) * | 1999-07-16 | 2002-09-24 | Massachusetts Institute Of Technology | Silicon on III-V semiconductor bonding for monolithic optoelectronic integration |
US6492195B2 (en) * | 1999-12-24 | 2002-12-10 | Hitachi, Ltd. | Method of thinning a semiconductor substrate using a perforated support substrate |
US7148122B2 (en) * | 2004-08-24 | 2006-12-12 | Intel Corporation | Bonding of substrates |
US20060284247A1 (en) * | 2005-06-17 | 2006-12-21 | Godfrey Augustine | Novel method for integrating silicon CMOS and AlGaN/GaN wideband amplifiers on engineered substrates |
US20070155056A1 (en) * | 2005-12-30 | 2007-07-05 | Samsung Electronics Co., Ltd. | Silicon direct bonding method |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6468823B1 (en) * | 1999-09-30 | 2002-10-22 | California Institute Of Technology | Fabrication of optical devices based on two dimensional photonic crystal structures and apparatus made thereby |
US6933586B2 (en) * | 2001-12-13 | 2005-08-23 | International Business Machines Corporation | Porous low-k dielectric interconnects with improved adhesion produced by partial burnout of surface porogens |
US7206488B1 (en) * | 2004-09-22 | 2007-04-17 | The Board Of Trustees Of The Leland Stanford Junior University | Coupled photonic crystal resonator array arrangements and applications |
-
2009
- 2009-01-14 CN CN200980102158.7A patent/CN101999165B/en active Active
- 2009-01-14 CN CN201510504926.9A patent/CN105161429B/en active Active
- 2009-01-14 US US12/353,798 patent/US8129257B2/en active Active
- 2009-01-14 EP EP09703836.8A patent/EP2238614B1/en active Active
- 2009-01-14 WO PCT/US2009/030997 patent/WO2009094276A2/en active Application Filing
-
2012
- 2012-01-27 US US13/359,775 patent/US8664083B2/en active Active
-
2014
- 2014-02-17 US US14/181,774 patent/US9263513B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6455398B1 (en) * | 1999-07-16 | 2002-09-24 | Massachusetts Institute Of Technology | Silicon on III-V semiconductor bonding for monolithic optoelectronic integration |
US6492195B2 (en) * | 1999-12-24 | 2002-12-10 | Hitachi, Ltd. | Method of thinning a semiconductor substrate using a perforated support substrate |
US7148122B2 (en) * | 2004-08-24 | 2006-12-12 | Intel Corporation | Bonding of substrates |
US20060284247A1 (en) * | 2005-06-17 | 2006-12-21 | Godfrey Augustine | Novel method for integrating silicon CMOS and AlGaN/GaN wideband amplifiers on engineered substrates |
US20070155056A1 (en) * | 2005-12-30 | 2007-07-05 | Samsung Electronics Co., Ltd. | Silicon direct bonding method |
Non-Patent Citations (3)
Title |
---|
BOWERS ET AL.: "A technology for integrating active photonic devices on SOI waters", PROCEEDINGS OF 2006 INTERNATIONAL CONFERENCE ON INDIUM PHOSPHIDE AND RELATED MATERIALS, 5 June 2006 (2006-06-05), pages 218 - 221, XP008139215 * |
FANG ET AL.: "Electrically pumped hybrid AlGalnAs-silicon evanescenet laser", OPTICS EXPRESS, vol. 14, no. 20, 2 October 2006 (2006-10-02), pages 9203 - 9210, XP002457693 * |
PASQUARIELLO ET AL.: "Plasma-Assisted InP-to-Si Low Temperature Wafer Bonding", IEEE JOURNAL ON SELECTED TOPICS QUANTUM ELECTRONICS, vol. 8, no. 1, 2002, pages 118 - 131, XP008139205 * |
Also Published As
Publication number | Publication date |
---|---|
EP2238614B1 (en) | 2020-03-11 |
CN105161429A (en) | 2015-12-16 |
WO2009094276A2 (en) | 2009-07-30 |
US20120119258A1 (en) | 2012-05-17 |
EP2238614A4 (en) | 2015-04-29 |
US9263513B2 (en) | 2016-02-16 |
US20090194787A1 (en) | 2009-08-06 |
CN101999165A (en) | 2011-03-30 |
CN101999165B (en) | 2015-09-16 |
US20140159210A1 (en) | 2014-06-12 |
US8664083B2 (en) | 2014-03-04 |
US8129257B2 (en) | 2012-03-06 |
EP2238614A2 (en) | 2010-10-13 |
CN105161429B (en) | 2018-06-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2009094276A3 (en) | Vertical outgassing channels | |
WO2010002516A3 (en) | Low-cost double structure substrates and methods for their manufacture | |
WO2008121262A3 (en) | Glass-ceramic-based semiconductor-on-insulator structures and method for making the same | |
PT1985464E (en) | Construction plate, in particular floor panel and method for its production | |
WO2007140288A3 (en) | Formation of improved soi substrates using bulk semiconductor wafers | |
TW200710947A (en) | Method for the manufacture of a strained silicon-on-insulator structure | |
GB2488961A (en) | Thin-box metal backgate extremely thin SOI device | |
WO2006023594A3 (en) | High strain glass/glass-ceramic containing semiconductor-on-insulator structures | |
WO2013026847A3 (en) | Soundproofing assembly, in particular for a motor vehicle | |
WO2009102499A3 (en) | Isolated cmos and bipolar transistors, isolation structures therefor and methods of fabricating the same | |
WO2012010662A3 (en) | Process for direct bonding two elements comprising copper portions and dielectric materials | |
JP2011216780A5 (en) | ||
FR2923079B1 (en) | SUBSTRATES SOI WITH INSULATED FINE LAYER ENTERREE | |
WO2009092794A3 (en) | Object provided with a graphics element transferred onto a support wafer and method of producing such an object | |
SG160300A1 (en) | Method for manufacturing soi substrate | |
EP2202526A3 (en) | Mems sensor and mems sensor manufacture method | |
WO2012087660A3 (en) | Semiconductor device contacts | |
WO2011128446A3 (en) | Method for manufacturing a hermetically sealed structure | |
WO2013018016A3 (en) | A PROCESS FOR THE MANUFACTURE OF SEMICONDUCTOR DEVICES COMPRISING THE CHEMICAL MECHANICAL POLISHING OF ELEMENTAL GERMANIUM AND/OR Si1-XGeX MATERIAL IN THE PRESENCE OF A CMP COMPOSITION HAVING A pH VALUE OF 3.0 TO 5.5 | |
SG166738A1 (en) | Method for manufacturing soi substrate and soi substrate | |
WO2011061029A3 (en) | Silicon layers made of polymer-modified liquid silane formulations | |
TW200631078A (en) | A method of making a semiconductor structure for high power semiconductor devices | |
TW200735378A (en) | Split gate memory cell and method for fabricating the same | |
CN103943547A (en) | Enhanced absorption based method for preparing material-on-insulator | |
WO2012027243A3 (en) | Method and apparatus for bonding member |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 200980102158.7 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 09703836 Country of ref document: EP Kind code of ref document: A2 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2009703836 Country of ref document: EP |