WO1995012150A1

WO1995012150A1 - An apparatus adapted for external unit specific control and method used therefor

Info

Publication number: WO1995012150A1
Application number: PCT/US1994/010445
Authority: WO
Inventors: Ronald J. Vanderhelm; Gregory Funk; Denis Beaudoin
Original assignee: Motorola Inc.
Priority date: 1993-10-28
Filing date: 1994-09-16
Publication date: 1995-05-04
Also published as: CN1116005A; JPH08506680A; CA2151376A1; EP0676063A4; EP0676063A1; AU7956194A

Abstract

A wireless data modem (103), adapted for external unit specific control in accordance with unit specific characteristics, including a non-volatile memory (107) co-resident with a data transceiver for storing data representative of the data transceiver's specific characteristics, an interface (109) providing access to the data by an external controller (101), and further providing access to the data transceiver by the external controller (101) to facilitate control of the data transceiver in accordance with its specific characteristics.

Description

An Apparatus Adapted For External Unit Specific Control And Method Used Therefore

Field Of The Invention

This disclosure deals with but is not limited to devices having unit specific characteristics that are adapted for external control in accordance with such characteristics.

Background Of The Invention

Many devices today due to increased performance expectations, or economic concerns, or quality aspirations may have a number of characteristics that are or can be unit specific. These unit specific characteristics may be adjustable or settable to optimize certain performance metrics or alternatively optimize various performance metrics that are application specific. Such situations are almost a rule in the case of electronic devices or assemblies. For electronic assemblies, practitioners routinely include various adjustments to negate the impact of among others, component and manufacturing tolerances or to optimize other performance concerns. This together with pressures on product cost, size, and power or current drain, or manufacturability and so forth together with the flexibility inherent in large scale integration has encouraged the utilization of various electrically or digitally variable components such as potentiometers, capacitors, and the like. Along with the possibility of setting such components comes the task of remembering the settings in order that the electronic assembly- can be properly initialized or programmed or configured at each power up. This requires a non volatile memory such as read only memory (ROM) or programmable read only memory (PROM). Some such electronic assemblies furthermore have a processor to provide access to the ROM and further to provide access to the variable components for setting the component appropriately in accordance with the device or unit specific characteristic. In such circumstances programming the electronic assembly to operate according to its unit specific characteristic is straight forward and well known. However there is a class of devices that simply do not have the relative luxury of a dedicated processor due to severe constraints on size, current drain, or cost. Such devices here to fore either have not taken advantage of the utility offered by the above referenced techniques or have relied on approaches such as providing an external data base to a controller or processor when such processor is identified.

Clearly a need exists for an apparatus that is adapted for external control where such control is in accordance with unit specific characteristics.

Brief Description Of The Drawings

The features of the present invention which are believed to be novel are set forth with particularity in the appended claims. However, the invention together with further advantages thereof, may best be understood by reference to the accompanying drawings in which:

FIG. 1 is a block diagram of an electronic assembly in accordance with an embodiment of the instant invention,

FIG. 2 is an exemplary memory map illustrative of a host computer interface in the FIG. 1 embodiment, FIG. 3 is a detailed block diagram of an interface portion of the FIG. 1 embodiment,

FIG. 4 is a flow chart indicative of using the FIG. 3 interface to access information used to control the FIG. 1 embodiment, FIG. 5 is a flow chart indicative of a process using the FIG. 3 interface to update information used to control the FIG. 1 embodiment, and

FIG. 6 is a table illustrative of information that. may be accessed in accordance with the FIG. 5 and FIG. 6 process flow charts.

Detailed Description Of A Preferred Embodiment

Generally this disclosure deals with an assembly or device that has various unit specific parameters and is further adapted for external control by for example a controller such as a processor or host computer. This assembly includes a non-volatile memory that is collocated or co-resident with the assembly or device or portion requiring or having the unit specific parameters or characteristics and is adapted for storing information or data that is representative of the unit specific characteristics. Additionally, the assembly includes an interface function that is arranged to provide access to the information or data stored in the non-volatile memory as well as access to the assembly or device by an external controller. The external controller may then provide the device with the information indicative of the unit specific characteristics when this is required. In a preferred embodiment the interface function includes a

Personal Computer Memory Card International Association (PCMCIA) compatible interface' from a processor to the device. The interface function may be viewed as a first interface, coupled to the non-volatile memory and arranged to provide access to the data or information within the non-volatile memory by an external controller, and a second interface, coupled to the data transceiver and arranged to provide access to the data transceiver by the external controller so as to provide control, configuration, initialization, or other operating data in accordance with the information that may be unit specific.

A more detailed explanation and thus appreciation of the instant invention will be provided with reference to the Figures in which FIG. 1, depicts a device, specifically an electronic assembly (103) that includes an RF transceiver (105) that has unit specific characteristics and hence requires unit specific information, such as calibration or initialization information, etc. In a preferred embodiment the device (103) is a wireless data modem and the RF transceiver (105) is a data transceiver. The electronic assembly

(103) is coupled to a host computer (101) by a control bus (113). The host computer can access the RF transceiver (105) through an interface (109) that converts the host computer's signals at the control bus (113) to a signal that is compatible with and appropriate for the RF transceiver at an output (115). A nonvolatile memory, such as an electrically erasable programmable read only memory (EEPROM) (107), is included with or co-resident with the electronic assembly (103) to store any information that is specific to and representative of the unit specific characteristics for the co-resident device or unit, such as that needed for initialization, configuration, or operation. The interface (109) further converts the host computer signals at the control bus (113) to transfer data that is representative of the unit specific information or characteristics to or from the EEPROM (107) at an input (111). In a preferred embodiment the input (111) is a serial or 3 wire EEPROM interface or bus as is well known in the art. In sum, the interface function (109) includes a 3 wire serial EEPROM interface, a data buffer, and an automated transfer function all cooperatively arranged for providing access to the data and to the device or wireless data modem.

Referring to FIG. 2 for a more detailed explanation, the host computer (101) is provided access to the electronic assembly (103) in accordance with the exemplary memory map depicted. For the sake of avoiding needless detail and as an example, the host computer's (101) access to the interface (109) and further access to the EEPROM (107) will be focused on with the understanding that the access to the RF transceiver (105) is provided in a similar manner. The host computer memory map (201) includes EEPROM access registers (205) and RF transceiver control registers (203) that are located at addresses within the host computer's memory field. These EEPROM access registers (205 & 203) are reserved for transferring and storing information required to access and support the interface (109) at the control bus (113). Generally, this includes information such as control or status bits, addresses to be used for reading or writing, and data registers for writing and reading. Focusing on the access to the EEPROM, the EEPROM access registers (205) include a control register (207), an EEPROM address register (209), a write data register (211) which contains the data or op code to send to the EEPROM and a read data register (213) which contains the data accessed or read back from the EEPROM.

The control register (207) can be expanded as depicted to include a load control bit (215), which when set by the host computer (101), causes the access to the EEPROM to begin. A busy bit (217) can be read by the host computer to monitor the status of the access or transfer. Bits "E0" (219) and "El" (221) determine as depicted an intended transfer type (225), such as read or write an address or op code, etc. An abort bit (223), when set, cancels the transfer that is in progress and resets the EEPROM interface to a known or predetermined state. Additionally, in an alternative embodiment the control register (207) while still functioning as a control register is for various practical reasons a composite of bits some of which are physically located at different and distinct addresses.

Referring to FIG. 3 and continuing to focus on the interface to the EEPROM, a physical embodiment of this interface is depicted. This embodiment includes an address register (301), a write data register (303) and a control register all coupled to the

load input (335) and a shift input (337). A load bit (329) from the control register (305) triggers the serial or 3 wire EEPROM controller (313) to provide a clock signal at line (321) and serial data to the EEPROM through the serial data line (320). In the case of a read operation or access, the 3 wire EEPROM controller (313) also controls at input (339) a serial to parallel shift register (311) which assembles information or data received from the EEPROM at a data output pin (322). The serial to parallel shift register (311) is coupled to the host computer at control bus (113). The EEPROM controller (313) asserts a "busy" status or busy signal at output (317) that may be accessed by the host computer (101) when it is in the process of performing a function. Additionally an "abort" status may be asserted by the host computer (101) at input (331).

The remaining function of the interface (109), specifically providing access to the RF transceiver, will now be briefly described. The control bus (113) is further coupled to a plurality of transceiver interface registers, including by way of example a power output register (351) and a DC offset register (355). This plurality of registers including registers (351) and 355) are used to store information provided by the host computer and each, respectively, has an output (353....357) that is interfaced with or coupled to and provides information to the RF transceiver (105) that is representative of the unit specific characteristics of that RF transceiver. Many of the interfaces, such as a digital to analog conversion etc., performed by the plurality of registers and the specifics of how they are performed are known. As an example of one interface that is in itself perhaps not unique but nevertheless is used advantageously by an embodiment that is inventive, the reader is referred to co-pending application PD05069AV - Walczak having a like filing date and assigned to the same assignee as here.

It should be understood that the FIG. 3 diagram is a simplified diagram and that the control bus (113) includes an address function as well as a data function. The address functions (not specifically shown) as are well known include an address decoder circuit that in turn provides an enable input to any register whose address has been decoded thus enabling that register to load or output data that is then available on the data function portion of the control bus (113). Referring to the FIG. 4 flow chart, an illustration of the process followed by the host computer to read data from the EEPROM is depicted and begins at step (401) with the control register bits "E0" and "El" (219 and 221) set to respectively "0" and "1" (signifying read address). The host computer (101) checks the status of the busy bit (217) at step (403) and when it is equal to "0", signifying not busy, loads the address register (301) with the location of the data within the EEPROM at step (405). This is the address within the EEPROM (107) that contains the data or information or unit specific information that is required. At step (407) the load bit is set and this causes the EEPROM controller (313) to initiate access to the EEPROM at the address as above described and to assert the busy signal at the output (317). The data at this EEPROM address will be provided to the serial to parallel shift register (311). When the data has all been serially received at the serial to parallel shift register (311) the EEPROM controller (313) will release the busy. The host computer (101) can determine this by checking the busy bit at step (409) and when the busy bit equals "0" accessing the data from the serial to parallel shift register (311). At step (411) if more data is required the process repeats from step (403) until all required data is retrieved. Then at step (412) the data is written to the appropriate RF transceiver control registers (203).

Referring to FIG. 6 some exemplary unit specific information or data is shown together with an address or location within EEPROM where the data is located. Thus, for example, if the RF transceiver or wireless data modem was initially being powered up the host computer (101) may access, in accordance with the above descriptions, EEPROM locations or addresses 00, 01, 02, and 03 to obtain unit specific information representing respectively a transceiver output power level, a varactor tuning setting, a frequency deviation setting, and a DC offset setting.

Referring to FIG. 5 a simplified illustration of the process used by the host computer (101) to update the unit specific information within the EEPROM is depicted and starts at step (501) with the control register in a write address state, specifically bits "E0" and "El" (219 and 221) respectively equal to "1" and "0". When the busy bit equals "0" at step (503) host computer (101) loads the address register (301) with the location of the unit specific information within the EEPROM at step (505). Similarly, at step (507), the write data register (303) is loaded with the unit specific information that is to be written to the EEPROM address or location from step (505). Following that the load bit (215) is set and the interface function of FIG. 3 updates the EEPROM (107) per the above discussion. Thus it will be appreciated by those of ordinary skill in the art that the apparatus and method disclosed herein provides an approach for facilitating external control in accordance with unit specific characteristics without relying on a co-resident processor with it's attendant cost, size, and power consumption disadvantages.

It will be apparent to those skilled in the art that the disclosed invention may be modified in numerous ways and may assume many embodiments other than the preferred form specifically set out and described above. Accordingly, it is intended by the appended claims to cover all modifications of the invention which fall within the true spirit and scope of the invention.

Claims

1. An assembly having unit specific parameters and adapted for external control, comprising in combination: a device having unit specific characteristics, a non-volatile memory co-resident with said device and adapted for storing a data that is representative of said unit specific characteristics, and an interface function, coupled to said device and said non- volatile memory, said interface function arranged to provide access to said data stored in said non-volatile memory and to provide access to said device by an external controller, said external controller then providing said device with said unit specific characteristics.

2. The assembly of claim 1 wherein said device includes a wireless data modem requiring initialization of an operating parameter.

3. The assembly of claim 2 wherein said operating parameter is a transmitter power setting.

4. The assembly of claim 2 wherein said interface function includes a Personal Computer Memory Card International Association (PCMCIA) compatible interface from a processor to an Electrically Erasable Programmable Read-Only Memory (EEPROM).

5. The assembly of claim 2 wherein said interface function includes a Personal Computer Memory Card International Association (PCMCIA) compatible interface from a processor to said wireless data modem.

6. A wireless data modem having unit specific parameters contained therewith and adapted for external control in accordance with the unit specific parameters, comprising in combination: a data transceiver having unit specific characteristics, a non-volatile memory co-resident with said data transceiver and adapted for storing an information representative of said unit specific characteristics, a first interface, coupled to said non-volatile memory, said interface arranged to provide access to said information by an external controller, and a second interface, coupled to said data transceiver, said second interface arranged to provide access to said data transceiver by said external controller to provide control in accordance with said information.

7. The wireless data modem of claim 6 wherein said unit specific characteristics include an operating parameter specific to said data transceiver.

8. The wireless data modem of claim 7 wherein said first interface includes a Personal Computer Memory Card International Association (PCMCIA) compatible interface from a processor to an Electrically Erasable Programmable Read-Only Memory (EEPROM).

9. The wireless data modem of claim 7wherein said second interface includes a PCMCIA compatible interface from a processor to said data transceiver.

10. In a wireless data modem having unit specific parameters contained therewith and adapted for external control in accordance with the unit specific parameters, a method including the steps of: providing unit specific characteristics for a data transceiver, storing, co-resident with said data transceiver, a information representative of said unit specific characteristics, providing access to said information by an external controller, and providing access to said data transceiver by said external controller to provide control in accordance with said information.